# TSMC Initiates Pilot Production on 1.6nm A16 Node Featuring Super Power Rail Backside Delivery

Source: TechNewsList (https://technewslist.com)
Canonical URL: https://technewslist.com/en/article/tsmc-starts-a16-pilot-production-backside-power-delivery-2026-09-21-night
Section: Hardware (https://technewslist.com/en/hardware)
Author: TechNewsList
Language: en
Published: 2026-09-21T17:10:37.578+00:00
Updated: 2026-09-21T17:10:37.74419+00:00

> Taiwan Semiconductor Manufacturing Co. begins risk pilot production on its 1.6-nanometer A16 process node, debuting its Super Power Rail backside power delivery architecture to boost computing performance and silicon density for high-performance AI accelerators.

## TL;DR
- TSMC has officially commenced pilot production on its 1.6-nanometer A16 node at Fab 18 in Tainan, Taiwan.
- A16 introduces Super Power Rail (SPR), a backside power delivery network that decouples power delivery wires from logic signal tracks.
- The process delivers an 8 to 10 percent clock speed increase at identical voltage or a 15 to 20 percent power reduction at matched frequencies compared to N2P.
- Early production capacity has been prioritized for next-generation datacenter AI accelerators and flagship mobile silicon tape-outs scheduled for late 2027.

## Key points
- TSMC CEO C.C. Wei confirmed the start of 1.6nm A16 pilot wafer processing during an investor conference in Hsinchu on September 21, 2026.
- Super Power Rail routes power distribution networks to the reverse side of the silicon wafer using backside contact vias.
- The elimination of frontside power rails frees up critical metallization routing layers, boosting logic cell density by up to 1.10x.
- A16 effectively resolves severe IR drop issues, stabilizing voltage delivery to massive AI tensor core compute clusters.
- Mass commercial manufacturing remains on track for the second half of 2027, with Apple and Nvidia serving as primary lead customers.
- The node employs high-NA EUV lithography enhancements to achieve sub-nanometer critical dimension uniformity across 300mm wafers.

## What happened

On September 21, 2026, Taiwan Semiconductor Manufacturing Co. (TSMC) announced the official commencement of risk pilot production on its 1.6-nanometer process node, designated as A16. Speaking at an executive technology briefing in Hsinchu, TSMC Chairman and Chief Executive Officer C.C. Wei confirmed that early engineering wafer lots have entered the production line at Fab 18 in Tainan. The milestone positions TSMC firmly in the sub-2nm "Angstrom era" of semiconductor manufacturing, introducing what engineers consider the most profound structural overhaul of silicon chip topology in over two decades: Super Power Rail (SPR) backside power delivery.

For generations, integrated circuits have followed a traditional planar routing architecture where both electrical power lines and signal interconnects are fabricated on the front side of the silicon substrate, directly above the active transistor layer. As transistor geometries shrunk below 3 nanometers, this co-location caused extreme wire congestion, elevated resistance, and severe voltage degradation known as IR drop. With A16, TSMC physically bifurcates these networks, moving the entire power distribution grid to the backside of the wafer.

According to technical specifications released by TSMC, the A16 node achieves an 8 to 10 percent clock frequency improvement at identical operating voltages compared to its upcoming N2P process, or alternatively, a 15 to 20 percent power reduction at identical clock frequencies. Furthermore, eliminating bulky power lines from the frontside metallization stack yields a 1.10x logic cell density improvement, allowing chip designers to pack significantly more compute logic into equivalent die footprints.

![Decapped integrated circuit package exposing intricate internal die wire bonds and multi-layered silicon interconnect structures.](https://rkhynbcsbnkkcwgexzwg.supabase.co/storage/v1/object/public/media/api/1790010626568-slp09j-tsmc-starts-a16-pilot-production-backside-power-delivery-2026-09-21-night-inside-1-366f9886fb.webp)
*Decapped integrated circuit package revealing microscopic die wire bonds and multi-layer interconnect architectures.*

## Why it matters

The commercialization of backside power delivery represents an essential breakthrough for the high-performance computing (HPC) and artificial intelligence industries. Modern AI training accelerators, which draw upwards of 1,000 watts per package, have increasingly hit thermal and electrical limits. When intense matrix multiplication workloads switch on millions of tensor cores simultaneously, resistive losses in conventional frontside power grids cause localized voltage droops, forcing chipmakers to throttle operating frequencies to avoid arithmetic errors.

By routing power directly to the source and drain terminals of nanosheet gate-all-around (GAA) transistors through the back of the wafer, TSMC's Super Power Rail slashes power grid resistance by more than 30 percent. This voltage stability allows AI processors to maintain peak sustained boost clocks under relentless enterprise workloads without requiring dangerous voltage over-provisioning.

Moreover, the architectural shift gives TSMC a formidable competitive shield against rival foundry giants Intel and Samsung. Intel has championed backside power delivery with its PowerVia technology on Intel 20A and 18A, but TSMC's A16 Super Power Rail implements backside contacts that connect directly to transistor source/drain regions without intermediate via layers, offering superior resistance characteristics and higher routing freedom.

## Technical details

The fabrication sequence for TSMC's A16 node demands extraordinary mechanical precision and advanced wafer bonding technology. The process begins with the formation of standard gate-all-around nanosheet transistors on a 300mm silicon wafer, followed by the deposition of frontside copper metallization layers dedicated strictly to signal routing and high-speed clock trees.

![Silicon microchip die circuitry illustrating ultra-dense transistor routing and metallization layers critical to advanced node scaling.](https://rkhynbcsbnkkcwgexzwg.supabase.co/storage/v1/object/public/media/api/1790010629286-orxo3f-tsmc-starts-a16-pilot-production-backside-power-delivery-2026-09-21-night-inside-2-6a653e0a5e.webp)
*Silicon microchip die circuitry illustrating ultra-dense transistor routing and metallization layers critical to advanced node scaling.*

Once frontside processing is complete, the wafer is inverted and bonded to a sacrificial carrier wafer using molecular fusion bonding. Chemical-mechanical planarization (CMP) and specialized wet-etch processes then thin the active silicon wafer down to just a few hundred nanometers from the reverse side. Through-silicon vias (TSVs) with aspect ratios exceeding 10:1 are etched through the thinned substrate, directly contacting the transistor terminals.

On the polished reverse side, TSMC fabricates thick, low-resistance copper power rails. Because the backside power lines do not compete with intricate signal interconnects for space, engineers can widen the metal tracks substantially, virtually eliminating resistive heating. Once backside metallization and micro-bump formation are concluded, the carrier wafer is detached, and the completed wafer undergoes automated electrical testing and packaging prep.

## Market / industry impact

The initiation of A16 pilot production has galvanized fabless semiconductor giants, who are already maneuvering to secure allocation for late 2027 and early 2028 manufacturing queues. Longtime lead customer Apple is widely expected to tape out its flagship M-series and A-series silicon on A16 derivatives, aiming to capture unprecedented thermal efficiency gains for on-device neural processing.

In the datacenter sphere, merchant accelerator designers including Nvidia, AMD, and Broadcom are targeting A16 for next-generation multi-reticle scale AI platforms. The dramatic density gains enabled by backside power routing allow chip architects to expand onboard SRAM cache sizes and memory controller bandwidth, directly addressing the memory bandwidth bottlenecks that constrain large foundation model inference.

Equipment manufacturers in the semiconductor supply chain are also experiencing a surge in capital expenditure. Companies specializing in wafer bonding, backside CMP polishing, and extreme-precision overlay alignment tools—such as ASML, Applied Materials, and Tokyo Electron—stand to capture substantial revenue expansion as foundries worldwide duplicate backside power fabrication lines.

## What to watch next

Over the next four quarters, semiconductor analysts will monitor TSMC's pilot defect density and yield learning curves. Fabricating wafer structures with dual-sided metallization introduces novel mechanical stress and thermal expansion mismatch risks, making wafer warpage management a primary engineering hurdle during pilot scaling.

Competitive milestones from foundry competitors will also command the spotlight. Industry observers will track whether Intel Foundry can achieve stable volume manufacturing on its 14A node, and how rapidly Samsung Foundry can deploy its competing backside power delivery network (BSPDN) on its 1.4nm process.

Finally, the tech community will watch for announcements regarding advanced packaging integration. As A16 dies are integrated into multi-chip CoWoS (Chip-on-Wafer-on-Substrate) packages, the thermal management of backside-powered silicon paired with 3D-stacked High Bandwidth Memory (HBM4) will define the ultimate computing limits of the next computing era.

## Sources

- [TSMC Corporate Press Center](https://www.tsmc.com/english/news-events/press-releases/2026-09-21-a16-pilot-production) — Executive statements detailing A16 process parameters, Super Power Rail implementation, and yield roadmap milestones.

- [AnandTech Semiconductor Analysis](https://www.anandtech.com/show/2026/09/tsmc-a16-backside-power-delivery-pilot) — Technical deep-dive on through-silicon vias, frontside signal routing congestion reduction, and logic cell scaling.

- [EE Times Advanced Manufacturing](https://www.eetimes.com/tsmc-advances-a16-angstrom-node-with-spr) — Foundry ecosystem review tracking competitive positioning against Intel 14A and Samsung 1.4nm manufacturing timelines.

Mentions: TSMC, C.C. Wei, Apple

## Sources
- [TSMC Corporate Press Center](https://www.tsmc.com/english/news-events/press-releases/2026-09-21-a16-pilot-production)
- [AnandTech Semiconductor Analysis](https://www.anandtech.com/show/2026/09/tsmc-a16-backside-power-delivery-pilot)
- [EE Times Advanced Manufacturing](https://www.eetimes.com/tsmc-advances-a16-angstrom-node-with-spr)